The present invention relates to a frequency multiplier without spurious oscillation, and particularly, to a frequency multiplier producing a microwave or a millimeter wave signal having double or quadruple the frequency of an incoming fundamental microwave signal of the order of 10 GHz or higher.
FIG. 14 is a circuit diagram showing a balanced frequency multiplier disclosed in JP No. 2807508.
This frequency multiplier includes a common source FET 10 and a common gate FET 11, wherein the gate G, as the input, of the FET 10 and the source S, as the input, of the FET 11 are both coupled to an input transmission line 12, and the drain D, as the output, of the FET 10 and the drain D, as the output, of the FET 11 are both connected directly to an output transmission line 13.
A dc cutoff capacitor 14 is connected between the gate G of the FET 10 and the input transmission line 12, and a reactance element 15 producing a phase lag is connected between the source S of the FET 11 and the input transmission line 12.
In order to operate the FETs 10 and 11 near the pinch-off, dc bias voltages are applied to respective gates of the FETs 10 and 11 from respective constant-voltage power sources 16 and 17 through respective resistances 18 and 19. A dc cutoff capacitor C is connected between the gate of the FET 11 and ground.
When a sine wave is provided to a microwave input terminal T1, the FET 10 rectifies the positive half cycles of the sine wave, while the FET 11 rectifies the negative half cycles of the sine wave and inverts the polarity thereof. Thereby, a fundamental and odd harmonics included in the drain current of the FET 10 are in opposite phase to respective those of the FET 11, and they are mutually canceled at an output terminal T2. In contrast to this, since even harmonics included in the drain current of the FET 10 are in phase with those of the FET 11, they are mutually enhanced at the output terminal T2. The amplitude of the fourth harmonic is considerably smaller than that of the second harmonic.
By properly determining the impedance of the reactance element 15, it is possible to prevent shifts from being in phase and in opposite phase at the output terminal T2, caused by a difference in transmission characteristics between the FET 10 and the FET 11.
According to the frequency multiplier of FIG. 14, since it is not required to provide a hybrid circuit for producing a pair of fundamentals in opposite phase from an incoming fundamental microwave signal, the frequency multiplier has an advantage in downsizing.
However, the present inventors found that this frequency multiplier has a below problem when it receives a microwave having a frequency of the order of 10 GHz or higher.
That is, when the input frequency exceeds the order of 10 GHz and as a result, the output frequency exceeds 20 GHz, then the common gate FET 11 comes to show unstableness such as a negative resistance at the gate G or the drain D thereof. In this case, it was not possible to prevent a spurious oscillation from occurring although an attenuator was connected near the output terminal T2 as a countermeasure.
It has been a common practice that in design of the above described frequency multiplier, a stub is connected to the drain D of the FET 11 to supply a dc bias and furthermore, impedance matching is achieved such that the output is maximized in regard to a target multiplied frequency.
However, there arises oscillation due to a combination of the stub and the negative resistance or due to a closed loop including the FETs 10 and 11. The spurious oscillation becomes remarkable especially in a case where a matching between the output of the frequency multiplier and an output buffer amplifier connected thereto is seriously poor (a reflection coefficient is a value close to 1).
Further, when realizing a frequency multiplier by 4 with deleting the second harmonic, an output frequency comes into a millimeter waveband, therefore it is required to employ the common gate FET 11 having a high performance (the maximum oscillating frequency fmax, or the maximum response frequency, is high) sufficient to realize the frequency multiplier by 4, resulting in that the negative resistance or a reflection gain of the common gate FET 11 becomes larger, which makes the above problem more serious.
Causes by which the negative resistance arises are a parasitic inductance of a conductor for grounding the gate G of the FET 11 and a tiny parasitic feedback capacitance between the drain D and the source S of the FET 11. Since the common gate FET especially has its output signal in phase with its input signal, the parasitic inductance forces the common gate FET 11 to produce positive feedback (in a common source FET whose output signal is in opposite phase with its input signal, negative feedback is produced and the common source FET is usually employed in a low-noise amplifier).
In formation of a common gate FET, it is indispensable to form a kind of lead for grounding, such as a bonding wire, a via formed in a substrate, or a lead up to the grounded conductor of a co-planar line. Alternatively, there is available a method of grounding by forming a xc2xc wavelength transmission line with an open end on a substrate. However, since grounding is achieved only for a given frequency component or band, the parasitic inductance arises except for the given frequency component or band.
Consequently, there have been a problem that a circuit including a common gate FET is rendered unstable with ease in a millimeter waveband or a high frequency waveband close thereto since it is hard to decrease the parasitic inductance to such a small value that no unstableness is brought about for all frequencies in operation of a common gate FET.
Accordingly, it is an object of the present invention to provide a stable frequency multiplier without spurious oscillation due to a inevitable parasitic inductance of a conductor for grounding a control input of a transistor.
In one aspect of the present invention, there is provided a frequency multiplier comprising: a first damping resistance, connected between a first end of the current path of a first transistor and an output transmission line; and a second damping resistance, connected between a first end of the current path of a second transistor and the output transmission line. Each of a second end of the first current path and a control input of the second transistor is grounded through a conductor having an inevitable parasitic inductance. The control input of the first transistor and the second end of the second current path receive microwaves of the same frequency and phase through an input transmission line.
With this configuration, when the input transmission line receives a sine microwave, the first transistor rectifies the positive half cycles of the sine microwave, while the second transistor rectifies the negative half cycles thereof and inverts their polarity. Thereby, the fundamentals and the odd harmonics on the output transmission line coming from the first and second current paths are in opposite phase and canceled by each other. In contrast to this, the even harmonics on the output transmission line coming from the first and second current paths are in phase and enhanced by each other.
Although the amplitudes of the waves passing through the first and second damping resistances are reduced, no shift in phase occurs. Hence, the even harmonics in phase are enhanced on the output transmission line.
The negative resistance is produced by the parasitic inductance of the conductor grounding the control input of the second transistor. However, the second damping resistance negates the formation of a pseudo-oscillating circuit comprising the second transistor and the output transmission line. That is, a loss on the output transmission line functioning as a resonator of the pseudo-oscillating circuit can be increased to nullify the establishment of oscillating conditions at an any frequency. Hence, even if design parameters are determined so as to produce a wave having a multiplied high frequency such as a millimeter wave, a stable frequency multiplier having none of spurious oscillation can be realized.
In a case where a possibility exists that oscillation occurs in a loop including the first and second transistors, a loop oscillation can be suppressed by determining the values of the first and second damping resistances such that a loop gain is less than 1.
Further, since an attenuator can be constituted of a combination of series and parallel resistances, by connecting a resistance between ground and a connection point among the first and second damping resistances and the output transmission line, impedance matching between the frequency multiplier and an output buffer amplifier connected to the output transmission line can be improved or a level diagram of the whole circuit including the frequency multiplier and the amplifier can be adjusted.
Since a bias current is provided through the first and second damping resistances to the current paths of the first and second transistors, voltage drops arise on the first and second damping resistances, and when one of the first and second transistors is in an ON state and the other is in an OFF state, the voltage of the current path of the ON state transistor is lower than the dc bias voltage thereof, while the current path of the OFF state transistor is maintained at a voltage almost equal to the dc bias voltage thereof. The voltage drop of the current path of the ON state transistor is larger as the value of the damping resistance increases. However, since the first and second transistors are biased near the respective threshold voltages, average current values flowing through the transistors are as low as, for example, 10 milliampere or lower, the voltage drop is 0.3 V at most when the damping resistance value is 30 ohm or less, and the loss of a frequency multiplying efficiency at the first and second transistors can be neglected.
According to a frequency multiplier of the present invention, a stable operation can be performed even there exists an inevitable parasitic inductance due to grounding conductor, a monolithic microwave integrated circuit (MMIC) can be realized in which a frequency multiplier, a fundamental oscillator at the preceding stage of the frequency multiplier, and an amplifier at the succeeding stage of the same are integrated on one chip having a ground plane formed on the back surface thereof.
Other aspects, objects, and the advantages of the present invention will become apparent from the following detailed description taken in connection with the accompanying drawings.